module choose( 
			input wire [2:0] cs_in,  // 数码管片选
			input wire [3:0] num_in,
			output reg [4:0] cs_out, // 数码管片选
			output wire [6:0] dig);


always @(*)
	case(cs_in)
		0: cs_out = 5'b11110;
		1: cs_out = 5'b11101;
		2: cs_out = 5'b11011;
		3: cs_out = 5'b10111;
		4: cs_out = 5'b01111;
	   default: cs_out= 4'b11111; // 0
	endcase

hex8 my_hex(.x(num_in), .dig(dig));
endmodule 